内推职位 - NVIDIA

职位1

ASIC Verification Engineer -

New College Grad

Durham, NC

Job ID: FL17722921

Summary

KEY RESPONSIBILITIES

Verify the design and implementation of the industry’s leading processor for deep learning, gaming, HPC and supercomputing.
Work on verifying a complex core ASIC design in a UVM testbench using advanced verification methodologies. You are expected to understand the design and verify its correctness.
Depending on the stage of the project, the job could involve test-planning, test-bench architecture, test-bench coding, coverage writing and closure, debugging among others.

BASIC QUALIFICATIONS

You are pursuing a Bachelor or Masters degree in EE or CS.
Exposure to verification languages (System Verilog or equivalent) and methodologies (UVM or equivalent) is a bonus.
Experience with Object Oriented programming (C++) and some exposure to Perl and/or Python.
Background with high-speed IO protocols like PCIE/CXL are a bonus.
Good debugging and problem-solving skills.

职位2

Software Engineer, Deep Learning Inference Workflows

- New College Grad

Santa Clara， CA

Job ID: FL1772922

Summary

KEY RESPONSIBILITIES

Develop components of TensorRT, NVIDIA’s SDK for high-performance deep learning inference.
Use C++ and Python to build graph parsers, optimizers, and tools for effective deployment of trained deep learning models.
Collaborate with teams of deep learning experts, GPU architects and DevOps engineers across diverse teams.

BASIC QUALIFICATIONS

BS, MS, PhD or equivalent experience in Computer Science, Computer Engineering.
Proficiency in C++.
Strong grasp of Machine Learning concepts.
Excellent communication skills, and an aptitude for collaboration and teamwork.

职位3

System Design and CAD Intern - Fall 2021

Santa Clara， CA

Job ID: FL1772923

Summary

KEY RESPONSIBILITIES

Define and develop highly configurable internal EDA software.
Define and automate flows and methodologies to efficiently build and verify generated RTL, Schematics and Netlists.
Verify the generated netlist in multiple environments (functional, RTL checks like lint and connectivity) and propagation of properties.
Work with EDA vendor tools (as needed) as well as industry standard scripting languages (Perl/Python, Make etc.).
Work with different teams to develop and support the flows.

BASIC QUALIFICATIONS

Minimum GPA 3.5.
Currently enrolled in MSEE or PhD.
Experience in RTL design (Verilog), Board/System implementation flow (Schematic/Layout), or design automation is highly desired.
Strong coding skills in Perl/Python or other industry-standard scripting languages.
Experience in object oriented programming desired.
Excellent debugging and analytical skills.
Exposure to verification and synthesis tools is a plus.

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