ISSCC 热点回顾
关于ISSCC
• ISSCC全称为International Solid State Circuits Conference，国际固态电路会议，是全球学术界和企业界公认的集成电路设计领域最高级别会议，有着“集成电路领域的奥林匹克”之称，每年吸引了超过3000名来自世界各地工业界和学术界的参与者。
•首届ISSCC于1954年在美国宾夕法尼亚州的费城召开。为纪念起源，即使在如今的ISSCC的logo上仍然印有University of Pennsylvania 。第一届ISSCC仅有六家学术机构投稿——贝尔实验室、通用电气、美国无线电公司（RCA）、费城电池公司（Philco）、麻省理工以及宾夕法尼亚大学。在ISSCC 60余年的历史里，众多集成电路历史上里程碑式的发明都是在这上面上首次披露。
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2013年-2022年，中国作者高被引发文
2022年
本届会议主题为Intelligent Silicon for a Sustainable World，相较于2021年，该年论文涉及的各个技术领域的比例大致不变，其中存储器领域略有提升，无线传输领域略有下降。
  • A 512Gb In-Memory-Computing 3D-NAND Flash Supporting Similar-Vector-Matching Operations on Edge-AI Devices
  • A 0.004mm2 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp
  • A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications
2021年
由于疫情，本届ISSCC第一次在线上举行，在ISSCC 2021论文的12个技术分类中，论文数量比较多的是高速网络、5G、WiFi、影响应用和机器学习。
  • 4.5 BioAIP: A Reconfigurable Biomedical AI Processor with Adaptive Learning for Versatile Intelligent Health Monitoring
  • 15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating
  • 15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization
2020年
本届会议的主题为“集成电路为人工智能时代赋能”，人工智能依旧还是最热门的主题。除了主题演讲之外，本届会议还有多个会场和人工智能相关，这些会场包括了高性能机器学习、低功耗机器学习、内存内计算以及基于非易失性存储器的下一代架构。
  • 33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing
  • 33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models
  • 15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips
2019年
在本届ISSCC会议中，AI芯片相关的论文占据总论文数接近10%，在这一年相关的AI芯片论文中，主要还是面向终端计算，以提升计算效率为主。
  • 24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning
  • 24.4 Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation
  • 4.2 A Broadband Switched-Transformer Digital Power Amplifier for Deep Back-Off Efficiency Enhancement
2018年
本届会议展示了国际集成电路在模拟电路、电源管理、数据转换器、数字电路及系统、存储器、 图像, MEMS, 医疗和显示 、有线通讯、射频和无线通讯和前瞻技术领域各热点方向的最新技术、产业进展及其设计最新发展趋势。
  • A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors
  • A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS
  • A 500mA analog-assisted digital-LDO-based on-chip distributed power delivery grid with cooperative regulation and IR-drop reduction in 65nm CMOS
2017年
本届会议的主题是“Intelligent Chips for A Smart World”，从中可以鲜明地看出两个技术潮流——即物联网和人工智能。
  • 20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control
  • 15.5 Cryo-CMOS circuits and systems for scalable quantum computing
  • 13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications
2016年
本届会议中“高效能”为数字集成电路设计的主要议题，人工智能、机器学习成为数字集成电路研究的新热点。
  • 4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
  • 3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
  • 21.3 A 200nA single-inductor dual-input-triple-output (DITO) converter with two-stage charging and process-limit cold-start voltage for photovoltaic and thermoelectric energy harvesting
2015年
  • 20.5 A 2-/3-phase fully integrated switched-capacitor DC-DC converter in bulk CMOS for energy-efficient digital circuits with 14% efficiency improvement
  • 20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors
  • 12.8 Wireless power transfer system using primary equalizer for coupling- and load-range extension in bio-implant applications
2014年
  • 17.11 A 0.65ns-response-time 3.01ps FOM fully-integrated low-dropout regulator with full-spectrum power-supply-rejection for wideband communication systems
  • 4.3 An 87%-peak-efficiency DVS-capable single-inductor 4-output DC-DC buck converter with ripple-based adaptive off-time control
  • 23.1 A 0.15V-input energy-harvesting charge pump with switching body biasing and adaptive dead-time for efficiency improvement
2013年
  • An 82.4% efficiency package-bondwire-based four-phase fully integrated buck converter with flying capacitor for area reduction
  • A 210GHz fully integrated differential transceiver with fundamental-frequency VCO in 32nm SOI CMOS
  • A 13.56MHz fully integrated 1X/2X active rectifier with compensated bias current for inductively powered devices
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