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 Verification Engineer
Westford, MA

Summary
NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Join our Memory Controller team and help build the real-time, cost-effective computing platform driving our success across several exciting and quickly growing fields.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate on the basis of race, religion, color, national origin, gender, gender expression , sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
As a Verification Engineer at NVIDIA, you will verify the design and implementation of our state of the art memory subsystem for our mobile SoCs and GPUs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. 
Description
  • In this position, you will be responsible for verification of memory subsystem design, architecture, golden models and micro-architecture using advanced verification methodologies.
  • As a member of our verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.
  • Collaborate with architects, designers, emulation and silicon verification teams to accomplish your tasks.
Key Qualifications
  • New College Grad.
  • Experience in architecting test bench environments for unit level verification.
  • Exposure to verification using random stimulus along with functional coverage and assertion-based verification methodologies.
  • Prior Design or Verification experience of dynamic memory controllers (ddr2, 3, 4, lpddr2, 3). Experience with interface characterization post-silicon is required.
  • C++ programming language experience, scripting ability and an expertise in System Verilog.
  • Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).
  • Strong debugging and analytical skills.
  • Strong communication and interpersonal skills are required. A history of mentoring junior engineers and interns a huge plus.
面试
  1. How do you achieve randc using rand?  
  2. Synchronize two systems with different clocks? Write code verilog?
  3. Explain NB assignment and blocking assignment. About event regions.  
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信息来源：
https://www.glassdoor.com
https://nvidia.com
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